mmRLC_GPM_TIMER_INT_3_BASE_IDX 9303 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_GPM_TIMER_INT_3_BASE_IDX                                                                 1
mmRLC_GPM_TIMER_INT_3_BASE_IDX 5969 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_GPM_TIMER_INT_3_BASE_IDX                                                                 1
mmRLC_GPM_TIMER_INT_3_BASE_IDX 6213 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_GPM_TIMER_INT_3_BASE_IDX                                                                 1
mmRLC_GPM_TIMER_INT_3_BASE_IDX 6177 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_GPM_TIMER_INT_3_BASE_IDX                                                                 1