mmRLC_GPM_TIMER_INT_0_BASE_IDX 9291 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_GPM_TIMER_INT_0_BASE_IDX                                                                 1
mmRLC_GPM_TIMER_INT_0_BASE_IDX 5957 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_GPM_TIMER_INT_0_BASE_IDX                                                                 1
mmRLC_GPM_TIMER_INT_0_BASE_IDX 6201 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_GPM_TIMER_INT_0_BASE_IDX                                                                 1
mmRLC_GPM_TIMER_INT_0_BASE_IDX 6165 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_GPM_TIMER_INT_0_BASE_IDX                                                                 1