mmRLC_GPM_INT_DISABLE_TH0_BASE_IDX 9449 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_GPM_INT_DISABLE_TH0_BASE_IDX                                                             1
mmRLC_GPM_INT_DISABLE_TH0_BASE_IDX 6107 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_GPM_INT_DISABLE_TH0_BASE_IDX                                                             1
mmRLC_GPM_INT_DISABLE_TH0_BASE_IDX 6351 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_GPM_INT_DISABLE_TH0_BASE_IDX                                                             1
mmRLC_GPM_INT_DISABLE_TH0_BASE_IDX 6329 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_GPM_INT_DISABLE_TH0_BASE_IDX                                                             1