mmRLC_DYN_PG_STATUS 9366 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_DYN_PG_STATUS                                                                            0x4c4b
mmRLC_DYN_PG_STATUS 6022 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_DYN_PG_STATUS                                                                            0x4c4b
mmRLC_DYN_PG_STATUS 6266 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_DYN_PG_STATUS                                                                            0x4c4b
mmRLC_DYN_PG_STATUS 6242 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_DYN_PG_STATUS                                                                            0x4c4b
mmRLC_DYN_PG_STATUS 1142 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h #define mmRLC_DYN_PG_STATUS 0x3103
mmRLC_DYN_PG_STATUS 1283 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h #define mmRLC_DYN_PG_STATUS                                                     0x310b
mmRLC_DYN_PG_STATUS 1296 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h #define mmRLC_DYN_PG_STATUS                                                     0x310b
mmRLC_DYN_PG_STATUS 1396 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h #define mmRLC_DYN_PG_STATUS                                                     0xec4b
mmRLC_DYN_PG_STATUS 1396 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h #define mmRLC_DYN_PG_STATUS                                                     0xec4b