mmRCC_MARGIN_PARAM_CNTL1_BASE_IDX  367 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_offset.h #define mmRCC_MARGIN_PARAM_CNTL1_BASE_IDX                                                              2
mmRCC_MARGIN_PARAM_CNTL1_BASE_IDX 2707 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h #define mmRCC_MARGIN_PARAM_CNTL1_BASE_IDX                                                              2