mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX  187 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX                                                           2
mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX  785 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX                                                           2
mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX  437 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX                                                           2
mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX  427 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX                                                           2