mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX  127 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX                                                            2
mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX  725 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX                                                            2
mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX  377 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX                                                            2
mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX  367 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX                                                            2