mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX  769 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX  569 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX  207 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1