mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX  675 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX  483 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX  155 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX  169 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1