mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX  657 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX  471 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX  139 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX  159 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1