mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX  655 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX  469 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX  137 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX  157 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1