mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX  651 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX  465 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX  133 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX  153 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1