mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1165 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX                                                   0
mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX  893 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_offset.h #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX                                                   0
mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1165 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_offset.h #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX                                                   0
mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1173 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_offset.h #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX                                                   0