mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX  774 drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                                    0
mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX  279 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_offset.h #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                                    2
mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2307 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_offset.h #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                                    2
mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 4189 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_offset.h #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                                    2
mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2627 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                                    2