mmPA_UTCL1_CNTL2_BASE_IDX  373 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmPA_UTCL1_CNTL2_BASE_IDX                                                                      0
mmPA_UTCL1_CNTL2_BASE_IDX  367 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmPA_UTCL1_CNTL2_BASE_IDX                                                                      0
mmPA_UTCL1_CNTL2_BASE_IDX  363 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmPA_UTCL1_CNTL2_BASE_IDX                                                                      0