mmPA_UTCL1_CNTL1_BASE_IDX  371 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmPA_UTCL1_CNTL1_BASE_IDX                                                                      0
mmPA_UTCL1_CNTL1_BASE_IDX  365 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmPA_UTCL1_CNTL1_BASE_IDX                                                                      0
mmPA_UTCL1_CNTL1_BASE_IDX  361 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmPA_UTCL1_CNTL1_BASE_IDX                                                                      0