mmPA_SU_SC_MODE_CNTL_BASE_IDX 6399 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmPA_SU_SC_MODE_CNTL_BASE_IDX                                                                  1
mmPA_SU_SC_MODE_CNTL_BASE_IDX 4005 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmPA_SU_SC_MODE_CNTL_BASE_IDX                                                                  1
mmPA_SU_SC_MODE_CNTL_BASE_IDX 4257 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmPA_SU_SC_MODE_CNTL_BASE_IDX                                                                  1
mmPA_SU_SC_MODE_CNTL_BASE_IDX 4209 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmPA_SU_SC_MODE_CNTL_BASE_IDX                                                                  1