mmPA_SU_SC_MODE_CNTL 6398 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmPA_SU_SC_MODE_CNTL                                                                           0x0205
mmPA_SU_SC_MODE_CNTL 4004 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmPA_SU_SC_MODE_CNTL                                                                           0x0205
mmPA_SU_SC_MODE_CNTL 4256 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmPA_SU_SC_MODE_CNTL                                                                           0x0205
mmPA_SU_SC_MODE_CNTL 4208 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmPA_SU_SC_MODE_CNTL                                                                           0x0205
mmPA_SU_SC_MODE_CNTL 1102 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h #define mmPA_SU_SC_MODE_CNTL 0xA205
mmPA_SU_SC_MODE_CNTL  961 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h #define mmPA_SU_SC_MODE_CNTL                                                    0xa205
mmPA_SU_SC_MODE_CNTL  974 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h #define mmPA_SU_SC_MODE_CNTL                                                    0xa205
mmPA_SU_SC_MODE_CNTL 1056 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h #define mmPA_SU_SC_MODE_CNTL                                                    0xa205
mmPA_SU_SC_MODE_CNTL 1056 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h #define mmPA_SU_SC_MODE_CNTL                                                    0xa205