mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX 2409 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX                                                           0
mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX  369 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX                                                           0
mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX  363 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX                                                           0
mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX  359 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX                                                           0