mmPA_SC_MODE_CNTL_0_BASE_IDX 6461 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmPA_SC_MODE_CNTL_0_BASE_IDX                                                                   1
mmPA_SC_MODE_CNTL_0_BASE_IDX 4063 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmPA_SC_MODE_CNTL_0_BASE_IDX                                                                   1
mmPA_SC_MODE_CNTL_0_BASE_IDX 4315 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmPA_SC_MODE_CNTL_0_BASE_IDX                                                                   1
mmPA_SC_MODE_CNTL_0_BASE_IDX 4269 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmPA_SC_MODE_CNTL_0_BASE_IDX                                                                   1