mmPA_SC_LINE_CNTL_BASE_IDX 6603 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmPA_SC_LINE_CNTL_BASE_IDX                                                                     1
mmPA_SC_LINE_CNTL_BASE_IDX 4201 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmPA_SC_LINE_CNTL_BASE_IDX                                                                     1
mmPA_SC_LINE_CNTL_BASE_IDX 4453 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmPA_SC_LINE_CNTL_BASE_IDX                                                                     1
mmPA_SC_LINE_CNTL_BASE_IDX 4409 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmPA_SC_LINE_CNTL_BASE_IDX                                                                     1