mmPA_SC_ENHANCE_1_BASE_IDX 2415 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmPA_SC_ENHANCE_1_BASE_IDX                                                                     0
mmPA_SC_ENHANCE_1_BASE_IDX  379 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmPA_SC_ENHANCE_1_BASE_IDX                                                                     0
mmPA_SC_ENHANCE_1_BASE_IDX  373 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmPA_SC_ENHANCE_1_BASE_IDX                                                                     0
mmPA_SC_ENHANCE_1_BASE_IDX  369 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmPA_SC_ENHANCE_1_BASE_IDX                                                                     0