mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX 2379 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX                                                           0
mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX  353 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX                                                           0
mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX  347 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX                                                           0
mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX  341 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX                                                           0