mmPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX 6651 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX                                                             1
mmPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX 4249 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX                                                             1
mmPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX 4501 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX                                                             1
mmPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX 4457 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX                                                             1