mmPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX 6649 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX                                                             1
mmPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX 4247 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX                                                             1
mmPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX 4499 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX                                                             1
mmPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX 4455 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX                                                             1