mmPA_CL_NANINF_CNTL_BASE_IDX 6405 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmPA_CL_NANINF_CNTL_BASE_IDX                                                                   1
mmPA_CL_NANINF_CNTL_BASE_IDX 4011 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmPA_CL_NANINF_CNTL_BASE_IDX                                                                   1
mmPA_CL_NANINF_CNTL_BASE_IDX 4263 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmPA_CL_NANINF_CNTL_BASE_IDX                                                                   1
mmPA_CL_NANINF_CNTL_BASE_IDX 4215 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmPA_CL_NANINF_CNTL_BASE_IDX                                                                   1