mmPA_CL_CNTL_STATUS_BASE_IDX 2357 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmPA_CL_CNTL_STATUS_BASE_IDX                                                                   0
mmPA_CL_CNTL_STATUS_BASE_IDX  329 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmPA_CL_CNTL_STATUS_BASE_IDX                                                                   0
mmPA_CL_CNTL_STATUS_BASE_IDX  325 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmPA_CL_CNTL_STATUS_BASE_IDX                                                                   0
mmPA_CL_CNTL_STATUS_BASE_IDX  319 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmPA_CL_CNTL_STATUS_BASE_IDX                                                                   0