mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 7490 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 10149 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 9119 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2