mmOTG5_OTG_STATUS_VF_COUNT_BASE_IDX 7434 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmOTG5_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
mmOTG5_OTG_STATUS_VF_COUNT_BASE_IDX 10099 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmOTG5_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
mmOTG5_OTG_STATUS_VF_COUNT_BASE_IDX 9069 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmOTG5_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2