mmOTG5_OTG_H_TIMING_CNTL_BASE_IDX 7372 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmOTG5_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
mmOTG5_OTG_H_TIMING_CNTL_BASE_IDX 10041 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmOTG5_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
mmOTG5_OTG_H_TIMING_CNTL_BASE_IDX 9011 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmOTG5_OTG_H_TIMING_CNTL_BASE_IDX                                                              2