mmOTG5_OTG_DRR_CONTROL_BASE_IDX 7572 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmOTG5_OTG_DRR_CONTROL_BASE_IDX                                                                2
mmOTG5_OTG_DRR_CONTROL_BASE_IDX 10233 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmOTG5_OTG_DRR_CONTROL_BASE_IDX                                                                2
mmOTG5_OTG_DRR_CONTROL_BASE_IDX 9203 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmOTG5_OTG_DRR_CONTROL_BASE_IDX                                                                2