mmOTG5_OTG_COUNT_CONTROL_BASE_IDX 7438 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmOTG5_OTG_COUNT_CONTROL_BASE_IDX                                                              2
mmOTG5_OTG_COUNT_CONTROL_BASE_IDX 10103 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmOTG5_OTG_COUNT_CONTROL_BASE_IDX                                                              2
mmOTG5_OTG_COUNT_CONTROL_BASE_IDX 9073 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmOTG5_OTG_COUNT_CONTROL_BASE_IDX                                                              2