mmOTG3_OTG_COUNT_RESET_BASE_IDX 7004 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmOTG3_OTG_COUNT_RESET_BASE_IDX                                                                2
mmOTG3_OTG_COUNT_RESET_BASE_IDX 9677 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmOTG3_OTG_COUNT_RESET_BASE_IDX                                                                2
mmOTG3_OTG_COUNT_RESET_BASE_IDX 8647 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmOTG3_OTG_COUNT_RESET_BASE_IDX                                                                2