BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 102511 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                              0x15
BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 30246 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                              0x15