mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 6564 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 9245 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 8215 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2