mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX 6500 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX 9185 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX 8155 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX                                                              2