BIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR__CAP_PTR_MASK 102348 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h #define BIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR__CAP_PTR_MASK                                                         0xFFL
BIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR__CAP_PTR_MASK 30096 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h #define BIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR__CAP_PTR_MASK                                                         0x000000FFL