mmOPP_PIPE5_OPP_PIPE_CONTROL_BASE_IDX 6154 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmOPP_PIPE5_OPP_PIPE_CONTROL_BASE_IDX                                                          2
mmOPP_PIPE5_OPP_PIPE_CONTROL_BASE_IDX 8759 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmOPP_PIPE5_OPP_PIPE_CONTROL_BASE_IDX                                                          2
mmOPP_PIPE5_OPP_PIPE_CONTROL_BASE_IDX 7729 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmOPP_PIPE5_OPP_PIPE_CONTROL_BASE_IDX                                                          2