mmMPC_CRC_SEL_CONTROL_BASE_IDX 5496 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMPC_CRC_SEL_CONTROL_BASE_IDX                                                                 2
mmMPC_CRC_SEL_CONTROL_BASE_IDX 6815 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPC_CRC_SEL_CONTROL_BASE_IDX                                                                 2
mmMPC_CRC_SEL_CONTROL_BASE_IDX 5877 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPC_CRC_SEL_CONTROL_BASE_IDX                                                                 2