mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 7366 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x147f
mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 6388 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x147f