mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 7362 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x147d
mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 6384 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x147d