mmMPCC7_MPCC_TOP_SEL 6774 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC7_MPCC_TOP_SEL                                                                           0x132e
mmMPCC7_MPCC_TOP_SEL 5836 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC7_MPCC_TOP_SEL                                                                           0x132e