mmMPCC7_MPCC_MEM_PWR_CTRL_BASE_IDX 6799 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC7_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
mmMPCC7_MPCC_MEM_PWR_CTRL_BASE_IDX 5861 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC7_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2