mmMPCC3_MPCC_TOP_SEL_BASE_IDX 5458 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMPCC3_MPCC_TOP_SEL_BASE_IDX                                                                  2
mmMPCC3_MPCC_TOP_SEL_BASE_IDX 6639 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC3_MPCC_TOP_SEL_BASE_IDX                                                                  2
mmMPCC3_MPCC_TOP_SEL_BASE_IDX 5701 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC3_MPCC_TOP_SEL_BASE_IDX                                                                  2