mmMPCC3_MPCC_TOP_SEL 5457 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMPCC3_MPCC_TOP_SEL                                                                           0x1681
mmMPCC3_MPCC_TOP_SEL 6638 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC3_MPCC_TOP_SEL                                                                           0x12c2
mmMPCC3_MPCC_TOP_SEL 5700 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC3_MPCC_TOP_SEL                                                                           0x12c2