mmMPCC3_MPCC_SM_CONTROL 5465 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMPCC3_MPCC_SM_CONTROL                                                                        0x1685
mmMPCC3_MPCC_SM_CONTROL 6646 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC3_MPCC_SM_CONTROL                                                                        0x12c6
mmMPCC3_MPCC_SM_CONTROL 5708 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC3_MPCC_SM_CONTROL                                                                        0x12c6