mmMPCC3_MPCC_BOT_SEL_BASE_IDX 5460 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMPCC3_MPCC_BOT_SEL_BASE_IDX                                                                  2
mmMPCC3_MPCC_BOT_SEL_BASE_IDX 6641 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC3_MPCC_BOT_SEL_BASE_IDX                                                                  2
mmMPCC3_MPCC_BOT_SEL_BASE_IDX 5703 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC3_MPCC_BOT_SEL_BASE_IDX                                                                  2