mmMPCC2_MPCC_TOP_SEL_BASE_IDX 5426 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMPCC2_MPCC_TOP_SEL_BASE_IDX                                                                  2
mmMPCC2_MPCC_TOP_SEL_BASE_IDX 6605 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC2_MPCC_TOP_SEL_BASE_IDX                                                                  2
mmMPCC2_MPCC_TOP_SEL_BASE_IDX 5667 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC2_MPCC_TOP_SEL_BASE_IDX                                                                  2