mmMPCC2_MPCC_TOP_SEL 5425 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMPCC2_MPCC_TOP_SEL                                                                           0x1666
mmMPCC2_MPCC_TOP_SEL 6604 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC2_MPCC_TOP_SEL                                                                           0x12a7
mmMPCC2_MPCC_TOP_SEL 5666 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC2_MPCC_TOP_SEL                                                                           0x12a7