mmMPCC2_MPCC_SM_CONTROL 5433 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmMPCC2_MPCC_SM_CONTROL                                                                        0x166a
mmMPCC2_MPCC_SM_CONTROL 6612 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmMPCC2_MPCC_SM_CONTROL                                                                        0x12ab
mmMPCC2_MPCC_SM_CONTROL 5674 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmMPCC2_MPCC_SM_CONTROL                                                                        0x12ab